1. Technical Field
The present invention relates generally to electric circuits and in particular to data receivers. Still more particularly, the present invention relates to equalization-based data receivers.
2. Description of the Related Art
Most modern data transmission relies on high-speed input/output (I/O) electrical data transmission channels linking a data transmitter (or transceiver) and a data receiver (i.e., the receiving circuit of a transceiver). Typically, this channel has a nonlinear frequency/phase response due to non-ideal conditions, which affect (e.g., distorts, attenuates, etc.) the transmitted data propagating through the channel. These non-ideal conditions within the channel causes inter-symbol-interference (ISI), leading to timing uncertainties at the receiver and an increase in the bit error rate (BER). Those skilled in the art are familiar with electrical data transmission channels and the occurrence of ISI and other conditions, such as increased BERs.
To compensate for the channel induced ISI, equalization techniques are utilized. These equalization techniques typically consist of any combination of digital and/or analog, linear or non-linear filters. Among these different types of filters are finite impulse response (FIR) filters and infinite impulse response (IIR) filters. Other components utilized to assist in equalization include amplification stages in the signal driver and/or preamplifiers with programmable or fix pole/zero distribution. Nonlinear IIR filters (also known as decision feedback equalizers or DFE) exhibit a very high equalization capability. Because of the widespread use of at least one of these equalizers at the receiver end of the date transmission channel, the receiver may generally be referred to as an equalization-based receiver.
FIG. 1 illustrates a prior art DFE circuit, with circuit components represented by blocks. As shown, DFE comprises an input amplifier/buffer 103 which receives input data signal (input voltage) 101 and forwards the amplified input voltage to voltage summing node 105. Weighted voltages determined by the values of previously detected bits and their respective filter/feedback coefficients (k0 . . . km) 111a-m are also summed at this node 105. Voltage summing node 105 sums the voltage output (amplified input data signal) from the amplifier/buffer 103 with voltages across parallel branches of filter/feedback coefficients 111a-m. Filter/feedback coefficients (k0 . . . km) 111a-m are utilized to provide a multiplication factor for associated voltages of previously detected bits, and each coefficient is a programmable value.
The summed voltage is provided across edge clock latch 109 and a delay path comprising sampler and delay latch (sampling latch) 107 series connected to a sequence of delay elements (z.sup.-1) 113a-n (where n is illustrated as being m−1). Each of sampling latch 107 and delay elements 113a-n receive an input of the data clock 108 to enable synchronized operation of the DFE circuit. Edge latch 109 receives a clock input from edge clock 110 and produces edge value output 115. A second output, data output 117 is tapped off of the node between sampling latch 107 and the first of the sequence of series-connected delay elements (i.e., delay 113a). Both edge value output 115 and data output 117 are sent to data FIFO (not shown), phase detector (not shown) and further to the clock and data recovery (CDR) loop (also not specifically shown).
One aspect of the design of receivers on I/O links is that the sampling clock phase in the receiver has to be adjusted to sample the incoming bits at or close to the optimum phase position, e.g. where the signal energy of the bit is at its maximum. This sampling is an important/key component to achieve minimum bit error rate performance. It is not a coincidence therefore, that one of the key sources of complexity in equalization-based receivers is the number of samples per bit utilized. Reducing this complexity is critical, since it also results in a reduction in power consumption of the receiver and the amount of area allocated to components in transmission channels (or applications) that require receiver equalization. While conventional integration methods have been implemented to attempt to overcome this requirement, there still exists a problem with conventional integration in that a very small value may be obtained if the timing is wrong.